View ADC1443D200HD_8162828.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1. general description the adc1443d is a dual channel 14-bit analog-to-digital converter (adc) with jesd204b interface (which is backward compatible with the jesd204a interface) optimized for high dynamic performance and low power consumption at sample rates up to 185 msps. pipelined architecture and output error correction guarantee zero missing codes over the entire operating range. supplied from a single 1.8 v source, the adc1443d has jesd204b serial outputs over a configurable number of lanes (1 or 2). multiple device synchronization (mds) allows sample-accurate synchronization of the data outputs of multiple adc devices. it guarantees a maximum skew of one clock period between as many as 16 output lanes from up to eight adc1443d devices. an integrated serial peripheral interface (spi) allows easy configuration of the adc. the device also includes a programmable full-scale to allow a flexible input voltage range of 1 v (p-p) to 2 v (p-p). with an analog banwidth from the baseband to input frequencies of up to 1 ghz (typical), the adc1443d is ideal for use in undersampled multi-carrier, multistandard communication system applications. 2. features and benefits adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs rev. 4.4 ? 6 june 2014 product data sheet ? dual channel 14-bit resolution adc ? snr = 70.6 dbfs (typical); f s = 154 msps; f i = 190 mhz ? sampling rate up to 185 msps ? sfdr = 86 dbc (typical); f s = 154 msps; f i = 190 mhz ? jesd204b device subclass 0, 1 and 2 with harmonic clocking and deterministic latency support ? imd3 = 88 dbc (typical); f s = 154 msps; f i1 = 188.5 mhz; f i2 = 191.5 mhz ? adc multiple device synchronization (mds) ? analog input bandwidth of 1 ghz (typical) ? two jesd204b serial output lanes, up to 5 gbps typical ? pin to pin compatible with adc1413d series ? single 1.8 v supply ? typical power dissipation = 0.8 w; f s = 154 msps ? offset binary, two?s complement and gray output data ? power-down and sleep modes
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 2 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 3. applications 4. ordering information ? flexible input voltage range from 1 v (p-p) to 2 v (p-p) by 1 db steps ? industrial temperature range from ? 40 ? c to +85 ? c ? clock input divider from 1 to 8 supports harmonic clocking ? serial peripheral interface (spi) for configuration control and status monitoring ? duty cycle stabilizer (dcs) ? vfqfpn56 package; 8 ? 8 mm ? wireless infrastructure: lte, td-lte, wimax, mc-gsm, cdma, wcdma, td-scdma ? microwave backhaul transceivers ? software defined radio ? aerospace and defense communications and radar systems ? medical non-invasive scanners ? industrial signal analysis instruments ? scientific particle detectors ? general-purpose high-speed applications table 1. ordering information type number f s (msps) package name description version ADC1443D200HD 185 vfqfpn plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm psc-4449 adc1443d160hd 160 vfqfpn plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm psc-4449 adc1443d125hd 125 vfqfpn plastic thermal enhanced low profile quad flat package; no leads; 56 terminals; resin based; body 8 ? 8 ? 1.35 mm psc-4449
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 3 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 5. block diagram fig 1. block diagram adc a core pipelined t/h input stage adc b core pipelined t/h input stage adc1443d frame assembly serializer a spi output buffer a serializer b output buffer b scrambler a encoder 8-bit/10-bit a scrambler b encoder 8-bit/10-bit b 8-bit 8-bit inap inam inbp inbm 8-bit 8-bit 10-bit 10-bit syncbp sclk sdio scs_n syncbn cmlbn cmlbp cmlan cmlap 14-bit 14-bit reference and power management clock divider and duty cycle stabilizer otra otrb sysref clkp clkm vdda vddo agnd ognd vcma vcmb
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 4 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 6. pinning information 6.1 pinning fig 2. pin configuration (psc-4449)
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 5 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 6.2 pin description table 2. pin description symbol pin type [1] description inam 1 i channel a complementary analog input inap 2 i channel a analog input vcma 3 o channel a output common voltage dnc 4 - do not connect dnc 5 - do not connect agnd 6 g analog ground clkp 7 i clock input clkn 8 i complementary clock input agnd 9 g analog ground dnc 10 - do not connect dnc 11 - do not connect vcmb 12 o channel b output common voltage inbp 13 i channel b analog input inbm 14 i channel b complementary analog input vdda 15 p analog power supply vdda 16 p analog power supply sclk 17 i spi clock. internally connected to 50k ?? pull-down sdio 18 i/o spi data io. internally connected to 50k ?? pull-down (when used as input) scs_n 19 i spi chip select. internally connected to 50k ?? pull-up agnd 20 g analog ground dnc 21 - do not connect scr_en 22 i scrambler enable. internally connected to 50k ?? pull-up cfg0/otra 23 i/o configuration pin 0/out of range a (otra). internally connected to 50k ?? pull-down (when used as input) cfg1/otrb 24 i/o configuration pin 1/out of range b (otrb). internally connected to 50k ?? pull-down (when used as input) cfg2 25 i/o configuration pin 2. internally connected to 50k ?? pull-down (when used as input) cfg3 26 i/o configuration pin 3. internally connected to 50k ?? pull-down (when used as input) vddo 27 p digital output power supply agnd 28 g analog ground ognd 29 g digital output ground ognd 30 g digital output ground vddo 31 p digital output power supply cmlbp 32 o channel b output cmlbn 33 o channel b complementary output vddo 34 p digital output power supply ognd 35 g digital output ground ognd 36 g digital output ground
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 6 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. 6.2.1 start-up configuration because the maximum sampling clock of the adc1443d is 200 msps, care should be taken in case of harmonic clocking. if the input clock frequency is higher than 200 mhz, the clock divider must be set before providing the clock. in order to avoid any issue, it is recommended to start the device in power-down mode by setting the configuration pins to logic level ?1? (see t able 19 ). this can be done by adding for example a 1 k ?? pull-up resistor on cfg0, cfg1, cfg2 and cfg3. when the power supplies are set, the divider can be programmed by the use of the spi registers. then the device is powered on and the jesd204b configuration is set by the use of the spi registers (bits cfg_setup[3:0] in t able 42 ). vddo 37 p digital output power supply cmlan 38 o channel a complementary output cmlap 39 o channel a output vddo 40 p digital output power supply ognd 41 g digital output ground ognd 42 g digital output ground syncbp 43 i jesd204b sync synchronization signal from receiver syncbn 44 i complementary sync from receiver agnd 45 g analog ground vddo 46 p digital output power supply dnc 47 - do not connect sysrefp 48 i positive clock synchronization sysrefn 49 i negative clock synchronization vdda 50 p analog power supply agnd 51 g analog ground agnd 52 g analog ground vdda 53 p analog power supply dnc 54 - do not connect dnc 55 - do not connect vdda 56 p analog power supply agnd exp g expose pad table 2. pin description ?continued symbol pin type [1] description
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 7 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 7. limiting values 8. thermal characteristics [1] in compliance with jedec test board, in free air. 9. static characteristics table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage ? 0.3 +2.1 v v ddo output supply voltage ? 0.3 +2.1 v ? v dd supply voltage difference v dda ? v ddo ? 0.8 +0.8 v v i input voltage pins inp, inm, clkp and clkm; referenced to agnd ? 0.3 v dda + 0.3 v pins otr, scs_n, sdio, sclk, cfg, scr_en, sysrefp, sysrefn, syncbp, and syncbn; referenced to agnd ? 0.3 v ddo + 0.3 v v o output voltage pin vcm; referenced to agnd ? 0.3 v dda + 0.3 v pins cmlp, and cmln; referenced to ognd ? 0.3 v ddo + 0.3 v t stg storage temperature ? 55 +125 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient 66 vias [1] 22.7 k/w r th(j-c) thermal resistance from junction to case 66 vias [1] 9.3 k/w table 5. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda analog supply voltage 1.7 1.8 1.9 v v ddo output supply voltage 1.7 1.8 1.9 v i dda analog supply current f s = 185 msps; f i = 190 mhz - 321 391 ma i ddo output supply current f s = 185 msps; f i = 190 mhz - 169 198 ma
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 8 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs p tot total power dissipation f i = 190 mhz adc1443d125; f s = 125 msps - 0.71 0.9 w adc1443d160; f s = 154 msps - 0.8 1.0 w adc1443d200; f s = 185 msps - 0.9 1.1 w power-down mode - 10 - mw sleep mode - 115 - mw clock inputs: pins clkp and clkm (ac-coupled; peak-to-peak) v i(clk) clock input voltage lvpecl - ? 0.8 - v lvds - ? 0.35 - v sine differential ? 0.5 ? 1.25 - v lvcmos single - ? 0.6 - v c i input capacitance - 1.2 - pf logic inputs i il low-level input current absolute value - 30 - ? a i ih high-level input current absolute value - 70 - ? a c i input capacitance - 1.2 - pf pins sysrefp, sysrefn, syncbp, and syncbn (diffrential pins) v i(cm) common-mode input voltage 0.925 1.2 1.475 v v i(dif) differential input voltage 0.2 0.7 - v pins scs_n, sdio, sclk, scr_en ,cfg, syncbpand sysrefp (single ended) v il low-level input voltage 0 - 0.3v ddo v v ih high-level input voltage 0.7v ddo -v ddo v logic output: pins otra, otrb and sdio v ol low-level output voltage 0 - 0.2 v v oh high-level output voltage v ddo -0.2 - v ddo v digital outputs: pins cmlap, cmlan, cmlbp, and cmlbn v o(cm) common-mode output voltage default current - 1.4 - v v o(dif) differential output voltage default current; peak-to-peak - 800 - mv analog inputs: pins inp and inm i i input current - ? 5- ? a r i input resistance f i = 190 mhz - 400 - ? c i input capacitance f i = 190 mhz - 5 - pf v i(cm) common-mode input voltage v inp = v inm ;t amb = 25 ? c 0.8 0.9 1.0 v b i input bandwidth - 1 - ghz v i(dif) differential input voltage peak-to-peak; full-scale 1 - 2 v common-mode output voltage: pins vcma and vcmb v o(cm) common-mode output voltage i o(cm) =1ma - 0.9 - v i o(cm) common-mode output current t amb = 25 ? c--1ma table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 9 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] typical values measured at v dda = v ddo = 1.8 v; t amb = 25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda = v ddo = 1.8 v; v i(dif) = 2 v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. accuracy inl integral non-linearity f s = 153.6 msps; f i = 4.43 mhz - ? 1.43 ? 5.2 lsb dnl differential non-linearity f s = 185 msps; f i = 4.43 mhz; guaranteed no missing codes minimum typical value -0.49 ? 0.30 lsb maximum typical value +0.25 +0.37 lsb e offset offset error ? 20 - +20 mv e g gain error full-scale - 4.1 - % m g(ctc) channel-to-channel gain matching - 3.5 - % os offset spur measured at fs/2 with fs=160msps -82 dbc supply psrr power supply rejection ratio 100 mv (p-p) on v dda , 0.5 to 2mhz - -47 - db table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 10 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10. dynamic characteristics 10.1 dynamic characteristics table 6. dynamic characteristics [1] symbol parameter conditions adc1443d125 (f s = 125 msps) adc1443d160 (f s = 154 msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max ? 2h second harmonic level f i = 5 mhz - -87 - - -84 - - -85 - dbc f i = 70 mhz - -85 - - -82 - - -75 - dbc f i = 140 mhz - -92 - - -85 - - -80 - dbc f i = 170 mhz - -83 - - -83 - - -87 - dbc f i = 190 mhz - -82 - - -86 - - -83 - dbc f i = 230 mhz - -78 - - -80 - - -86 - dbc ? 3h third harmonic level f i = 5 mhz - -100 - - -88 - - -85 - dbc f i = 70 mhz - -97 - - -90 - - -81 - dbc f i = 140 mhz - -88 - - -89 - - -85 - dbc f i = 170 mhz - -94 - - -90 - - -83 - dbc f i = 190 mhz - -96 - - -87 - - -80 - dbc f i = 230 mhz - -95 - - -85 - - -80 - dbc sfdr spurious-free dynamic range f i = 5 mhz - 87 - - 84 - - 79 - dbc f i = 70 mhz - 85 - - 82 - - 75 - dbc f i = 140 mhz - 92 - - 85 - - 80 - dbc f i = 170 mhz - 83 - - 83 - - 83 - dbc f i = 190 mhz - 82 - - 86 - - 80 - dbc f i = 230 mhz - 78 - - 80 - - 80 - dbc thd total harmonic distortion f i = 5 mhz - -86.5 - - -82.3 - - -80 - dbc f i = 70 mhz - -84.2 - - -80 - - -72 - dbc f i = 140 mhz - -85.3 - - -82.8 - - -77 - dbc f i = 170 mhz - -81.8 - - -81.7 - - -80 - dbc f i = 190 mhz - -81.4 - - -81.9 - - -78 - dbc f i = 230 mhz - -77.5 - - -78.5 - - -78 - dbc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 11 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] typical values measured at v dda = v ddo = 1.8 v; t amb = 25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda = v ddo = 1.8 v; v i(dif) = 2 v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. imd3 third-order intermodulation distortion f i1 = 3.5 mhz; f i2 = 6.5 mhz - 91 - - 90 - - 85 - dbc f i1 = 68.5 mhz; f i2 = 71.5 mhz - 90 - - 89 - - 85 - dbc f i1 = 138.5 mhz; f i2 = 141.5 mhz - 89 - - 88 - - 84 - dbc f i1 = 168.5 mhz; f i2 = 171.5 mhz - 91 - - 88 - - 83 - dbc f i1 = 188.5 mhz; f i2 = 191.5 mhz - 88 - - 87 - - 87 - dbc f i1 = 228.5 mhz; f i2 = 231.5 mhz - 87 - - 87 - - 88 - dbc snr signal-to-noise ratio f i = 5 mhz - 72.6 - - 71.9 - - 68.8 - dbfs f i = 70 mhz - 72.4 - - 71.7 - - 68 - dbfs f i = 140 mhz - 72.1 - - 71.3 - - 68.3 - dbfs f i = 170 mhz - 71.6 - - 70.8 - - 68.5 - dbfs f i = 190 mhz - 71.2 - - 70.6 - - 68.5 - dbfs f i = 230 mhz - 70.6 - - 70 - - 67 - dbfs enob effective number of bits f i = 5 mhz - 11.7 - - 11.4 - - 10.9 - bit f i = 70 mhz - 11.7 - - 11.4 - - 10.7 - bit f i = 140 mhz - 11.7 - - 11.3 - - 10.8 - bit f i = 170 mhz - 11.5 - - 11.3 - - 10.9 - bit f i = 190 mhz - 11.5 - - 11.2 - - 10.8 - bit f i = 230 mhz - 11.3 - - 11.1 - - 10.6 - bit ? ct(ch) channel crosstalk f i = 140 mhz - 95 - - 95 - - 92 - dbc f i = 230 mhz - 90 - - 90 - - 92 - dbc table 6. dynamic characteristics [1] ?continued symbol parameter conditions adc1443d125 (f s = 125 msps) adc1443d160 (f s = 154 msps) adc1443d200 (f s = 185 msps) unit min typ max min typ max min typ max
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 12 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.2 timing 10.2.1 clock timing [1] typical values measured at v dda = v ddo = 1.8 v; t amb = 25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to 85 ? c at v dda = v ddo = 1.8 v; v i(dif) = 2 v; v inp ? v inm = ? 1 dbfs; unless otherwise specified. 10.2.2 sysrefp/n and syncbp/n timings table 7. clock and digital output timing characteristics [1] symbol parameter conditions min typ max unit t lat(data) data latency time f=1 54 - 55 clock cycles f=2 45.5 - 46 clock cycles f=4 41 - 41.25 clock cycles t wake wake-up time from power-down mode - 60 - s from sleep mode - 54 - s clock timing f s sampling rate adc1443d125 60 - 125 mhz adc1443d160 125 - 160 mhz adc1443d200 160 - 185 mhz f clk clock frequency 60 - 800 mhz ? clk clock duty cycle 40 - 60 % table 8. sysref timing symbol parameter conditions min typ max unit t su set-up time 0.5 - - ns t h hold time (tclk/2) -0.5 --ns table 9. syncb timing symbol parameter conditions min typ max unit t su set-up time 0.75 - - ns t h hold time (tclk/2) -0.25 --ns fig 3. sysref timing clkp-clkm sysref 50 % 70 % 70 % t su t h
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 13 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.2.3 spi timing [1] typical values measured at v dda = v ddo = 1.8 v; t amb = 25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda = v ddo = 1.8 v table 10. spi timing characteristics [1] symbol parameter conditions min typ max unit t w(sclk) sclk pulse width 40 - - ns t w(sclkh) sclk high pulse width 16 - - ns t w(sclkl) sclk low pulse width 16 - - ns t su set-up time sdio to sclk high 5 - - ns scs_n to sclk high 5 - - ns t h hold time sdio to sclk high 2 - - ns scs_n to sclk high 2 - - ns f clk clock frequency - - 25 mhz fig 4. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) s cs_n t w(sclkl) t w(sclkh)
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 14 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3 typical dynamic performances 1 10.3.1 typical fft at 122.88 msps 1. typical values measured at v dda = v ddo = 1.8 v; t amb = 25 ? c fig 5. 1-tone fft: ? 1 dbfs; f i = 50 mhz; f s = 122.88 msps fig 6. 1-tone fft: ? 1 dbfs; f i = 155 mhz; f s = 122.88 msps fig 7. 1-tone fft: ? 14 dbfs; f i = 155 mhz; f s = 122.88 msps fig 8. 2-tone fft: ? 7 dbfs; f i1 = 153.5 mhz; f i2 = 156.5 mhz; f s = 122.88 msps
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 15 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3.2 typical fft at 153.6 msps fig 9. 1-tone fft: ? 1 dbfs; f i = 50 mhz; f s = 153.6 msps fig 10. 1-tone fft: ? 1 dbfs; f i = 190 mhz; f s = 153.6 msps fig 11. 1-tone fft: ? 14 dbfs; f i = 190 mhz; f s = 153.6 msps fig 12. 2-tone fft: ? 7 dbfs; f i1 = 188.5 mhz; f i2 = 191.5 mhz; f s = 153.6 msps
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 16 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3.3 typical fft at 184.32 msps fig 13. 1-tone fft: ? 1 dbfs; f i =65 mhz; f s = 184.32msps fig 14. 1-tone fft: ? 1 dbfs; f i = 190 mhz; f s = 184.32 msps fig 15. 1-tone fft: ? 14 dbfs; f i = 190 mhz; f s = 184.32 msps fig 16. 2-tone fft: ? 7 dbfs; f i1 = 140 mhz; f i2 = 143mhz; f s = 184.32 msps
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 17 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3.4 typical snr performances fig 17. snr as a function of sampling frequency: ? 1 dbfs; f i = 170 mhz fig 18. snr as a function of input frequency: ? 1 dbfs fig 19. snr as a function of input amplitude: v i(dif) = 2 v fig 20. snr as a function of full-scale amplitude: ? 1 dbfs
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 18 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3.5 typical sfdr performances fig 21. sfdr as a function of sampling frequency: ? 1 dbfs; f i = 170 mhz fig 22. sfdr as a function of input frequency: ? 1 dbfs fig 23. sfdr as a function of input amplitude: v i(dif) = 2 v fig 24. sfdr as a function of full-scale amplitude: ? 1 dbfs
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 19 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 10.3.6 typical imd3 performances fig 25. imd3 as a function of sampling frequency: ? 7 dbfs; f i1 = 168.5 mhz; f i2 = 171.5 mhz fig 26. imd3 as a function of input frequency: ? 7 dbfs; 3 mhz spacing fig 27. imd3 as a function of input amplitude: 3 mhz spacing; v i(dif) = 2 v fig 28. imd3 as a function of full-scale amplitude: ? 7 dbfs; 3 mhz spacing
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 20 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11. application information 11.1 analog inputs 11.1.1 input stage the analog input of the adc1443d supports a differential or a single-ended input drive. optimal performance is achieved using differential inputs with respect to the common-mode input voltage (v i(cm) ) on pins inp and inm. the equivalent circuit of the sample and hold input stage, including electrostatic discharge (esd) protection circuit and package parasitics, is shown in figure 29 . the sample phase occurs when the internal sampling clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then held on the sampling capacitors. when the sampling clock signal becomes low, the device enters the hold phase and the voltage information is transmitted to the adc core. 11.1.2 common-mode input voltage (v i(cm) ) set the common-mode input voltage (v i(cm) ) on pins inp and inm externally to 0.9 v for optimal performance. 11.1.3 pin vcm when the input stage is ac-coupled, pin vcm can be used to set the common-mode reference for the analog inputs, for instance, via a transformer middle point. connect a 0.1 ? f filter capacitor between pin vcm and ground to ensure a low-noise common-mode output voltage. fig 29. input sampling circuit i np package esd parasitics switch r on = 15 4 pf 4 pf sampling capacitor sampling capacitor switch r on = 15 i nm internal clock internal clock
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 21 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.1.4 programmable full-scale the full-scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) by programming internal reference gain between 0 db and ? 6 db in 1 db steps. the full-scale range can be set independently via bits intref[2:0] of the spi local registers (see t able 1 1 and t able 30 ). 11.1.5 anti-kickback circuitry an anti-kickback circuitry (rc-filter in figure 31 ) is required to counteract the effects of the charge injection generated by the sampling capacitance. the rc-filter is also used to filter noise from the signal before it reaches the sampling stage. it is recommended that the capacitor has a value that maximizes noise attenuation without degrading the settling time excessively. fig 30. equivalent schematic of the common-mode reference circuit vcm 0.1 f package esd parasitics common mode reference adc core table 11. reference gain control default values are shown highlighted. intref[2:0] level (db) full-scale (v (p-p)) 000 0 2 001 ? 1 1.78 010 ? 2 1.59 011 ? 3 1.42 100 ? 4 1.26 101 ? 5 1.12 110 ? 61 111 reserved x
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 22 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs the input frequency determines the component values. select values that do not affect the input bandwidth. the values given in the following table are advised for 50 ? impedance system. 11.1.6 transformer the input frequency determines the configuration of the transformer circuit. the configuration shown in figure 32 is suitable for a baseband application. fig 31. anti-kickback circuit table 12. rc coupling versus input frequency; typical values input frequency range (mhz) r ( ? ) c (pf) 0 to 50 25 12 50 to 200 10 3.9 200 to 300 6.8 3 r r c inxp inxm fig 32. single transformer configuration (baseband) 100 nf 100 nf 100 nf 100 nf 25 25 25 25 12 pf inxp inxm vcmx 100 nf analog input 100 nf
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 23 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs the configuration shown in figure 33 is recommended for high-frequency applications. in both cases, the choice of transformer is a compromise between cost and performance. 11.2 clock input 11.2.1 drive modes the adc1443d series can be driven differentially (lvpecl, lvds or sine). a single-ended lvcmos signal connected to either pin clkp or pin clkm can also drive the device (connect the complementary pin to ground using a capacitor). the lvpecl is recommended for an optimal performance. fig 33. dual transformer configuration (high if) 100 nf 100 nf 100 nf 100 nf 10 10 3.9 pf inxp inxm vcmx 50 50 50 50 analog input fig 34. lvpecl/lvds differential clock input a. differential sine clock input b. single-ended sine clock input (with transformer) fig 35. sine clock input l vpecl / lvds clock input clkp clkm sine c lock input clkp clkm sine c lock input clkp clkm
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 24 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs single-ended or differential clock inputs can be selected via bit diff_se of spi. if single-ended is enabled, the input pin (pin clkm or pin clkp) is selected using control bit se_sel (see t able 29 ). 11.2.2 equivalent input circuit figure 37 shows the equivalent circuit of the input clock buffer. the input signal must be ac-coupled and the common-mode voltage of the differential input stage is set via internal 5 k ? resistors. 11.2.3 jesd204b harmonic clocking the adc1443d embeds an input clock divider that divides the incoming clock (clock frequency fclk) by a factor of 1 to 8. the output of this divider is then used as sampling clock (sampling frequency fs) (see bits clk_div[2:0] in t able 29 ). this feature allows a higher clock frequency to be delivered to the adc1443d,which ultimately leads to better jitter performance and better snr. the adc1443d should not be driven with a clock higher than 250msps if the cloc is not enabled, otherwise there is a risk of metastability. a. rising edge lvcmos b. falling edge lvcmos fig 36. lvcmos single-ended clock input lvcmos c lock input clkp clkm lvcmos c lock input clkp clkm fig 37. equivalent input circuit c lkp c lkm package esd parasitics 5 k v cm(clk) 5 k
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 25 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs caution must be taken to first, power the adc1443 in ? power down? mode by setting the cfg pins to ?1111? see t able 18 , second, program the clock divider to the wanted value (see bits clk_div[1:0] in t able 29 ) and finally, set the adc using the spi register ip_cfg_setup t able 42 , to the wanted configuration. 11.2.4 jesd204b deterministic latency (pins sysrefn and sysrefp or syncbp and syncbn) in the jesd204b standard 3 subclasses have been defined. subclass 0 : no deterministic latency is required (equivalent to the jesd204a) subclass 1 : deterministic latency is required and is realized through the dedicated sysrefp/n pins. the deterministic latency can be controlled with a single-ended or a differential sysref signal. when sysref is active (high by default), it resets the clock divider phase registers. in a multi-device application and when the clock divider factor is higher than 1, all sampling clock edges for multiple adc1443d will be aligned (see t able 8 and figure 3 ). on top of this, the sysrefp/n pins initiates an internal lmfc clock ( local multi-frame clock), with a frequency of a multi-frame (fs/k) ( k: number of frames per multi-frame) see table t able 18 for examples. at a sync request from the receiver (on pins syncbp/n), k28.5 comma characters are sent over the serial lanes. when the receiver releases the sync request, then the initial lane alignement (ila) will start at an edge of the lmfc at the receiver side, the different lanes are aligned using the ila start of frame c h and fetched at the next lmfc boundary. this operation ensures a deterministic latency. see the jesd204b jedec standard for more information. subclass2 : behaviour is similar to subclass1, but, instead of using a dedicated sysref signal, the syncbp/n is used for both sync request and deterministic latency. the rising edge of the syncbp/n start the lmfc, while the falling edge set the sync request and hence start the initial lane alignement according to the jedec jesd204b standard. below is an example of a subclass1 adc1443d registers programming : table 13. subclass1 path activation register value comment dcs_ctrl (@0x043) 0xc7 choose the sysrefp/n on rising edge as dcs reset jesd204b_ctrl1 (@810) 0xc0 enable an lmfc periodic reset jesd204b_ctrl2 (@811) 0x40 enable a one shot dcs reset jesd204b_ctrl3 (@812) 0x0a activate a sync fetch at lmfc boundary sysref_cfg (@81e) 0x08 enable sysrefp/n on differential mode
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 26 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.3 digital outputs 11.3.1 digital output buffers the jesd204a/jesd204b standard specifies that both the receiver and the transmitter must share the same supply if they are connected in dc-coupling. 11.3.2 jesd204a/jesd204b serializer 11.3.2.1 digital jesd204a/jesd204b formatter the block placed after the adc1443d cores implements all the jesd204a/jesd204b standard functionalities. this ensures signal integrity and guarantees the clock and the data recovery at the receiver side. the block is highly configurable in various ways depending on the sampling frequency and the number of lanes used.all the processing and transmission are done with msb first. fig 38. jesd204a/jesd204b serial output - dc-coupled fig 39. jesd204a/jesd204b serial output - ac-coupled vddo vddo cmlap/clmbp cmlan/clmbn ognd 12 ma to 26 ma 100 + receiver 50 - vddo cmlap/clmbp cmlan/clmbn 12 ma to 26 ma 100 10 nf 10 nf + receiver 50 -
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 27 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs fig 40. general overview of the jesd204a/jesd204b serializer frame to octets f octets scrambler tx transport layer cf: position of control bits hd: frame boundary break padding with tail bits (tt) mx(n'xs) bits lx(f) octets l octets n' = n+cs s samples per frame cycle samples stream to lane stream mapping n bits from cr 0 + cs bits for control n bits from cr m ? 1 + cs bits for control m converters l lanes lane 1 frame to octets f octets scrambler 8-bit/ 10-bit ser tx controller lane 0 8-bit/ 10-bit ser alignment character generator alignment character generator sync~ fig 41. detailed view of the jesd204a/jesd204b serializer with debug functionalities n and cs n and cs scr scr 8-bit/ 10-bit 8-bit/ 10-bit 8 8 n + cs n + cs 14 + 1 14 + 1 14 + 1 adc a pll and dll frame clk character clk bit clk 10 10 ser ser 11 10 00 11 10 00 dummy adc_pd adc_pd adc b prbs fsm (frame assembly, character replication; ila, test mode) frame assembly sync_request 14 + 1 adc_mode[1:0] lane_mode[1:0] lane_pol lane_mode[1:0] lane_pol 14 + 1 14 + 1 dummy prbs adc_mode[1:0] 1 f 10f
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 28 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.3.2.2 scrambler (scr_en) the main purpose of scrambling is to avoid the spectral peaks that would be produced when the same data octet repeats from frame to frame. in general, scrambling makes the spectrum data-independent, so that possible frequency-selective effects on the electrical interface will not cause data-dependent errors. however, all digital operations in converters (including scrambling) cause some amount of switching noise, so there may be applications where it is of advantage to disable the scrambling. th e scrambler can be selected via the pin scr_en or the spi registers (bit scr_en in t able 57 ). an internal pull-up resistor (50 k ? ) sets pin scr_en to high when no signal is connected to it. the pin scr_en is active only at start-up or after a jesd204b reset (bit scr_en in t able 41 ). 11.3.3 out-of-range (otr) an out-of-range signal is provided on pins otra and otrb.the otr signal goes logic level high when the input signal exceeds the maximum full scale range. the latency of otr is 31 clock cycles. the otr response can be speeded up by enabling fast otr using spi local registers (bit fast_otr in t able 37 ). in this mode, the latency of otr is reduced to only 11 clock cycles. the fast otr detection threshold (below full-scale) can be programmed using the spi local registers (bits fast_otr_det[2:0] in t able 37 ). 11.3.4 digital offset by default, the adc1443d delivers an output code that corresponds to the analog input. however, it is possible to add a digital offset to the output code using the spi local registers (bits dig_offset[5:0] in see t able 16 and t able 33 ). the digital offset adjustment is coded in two?s complement. table 14. scrambler configuration pin scr_en scrambler high enabled low disabled table 15. fast otr register threshold fast_otr_det[2:0] detection level (db) 000 ? 18.06 001 ? 14.54 010 ? 12.04 011 ? 8.52 100 ? 6.02 101 ? 4.08 110 ? 2.5 111 ? 1.16
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 29 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.3.5 test patterns the adc1443d can be configured to transmit a number of predefined test patterns using the spi local registers (bits test_pat_sel[2:0] in t able 17 and t able 34 ). the selected test pattern is transmitted regardless of the analog input. a custom test pattern can be defined using the spi local registers (bits test_pat_user[13:6] in t able 35 and bits test_pat_user[5:0] in t able 36 ). 11.3.6 output data format selection the adc1443d output data format can be selected (offset binary, two?s complement or gray code) using the spi local registers (bits data_format[1:0] in t able 32 ). 11.3.7 output codes versus input voltage table 16. digital offset adjustment default values are shown highlighted. dig_offset[5:0] digital offset adjustment (lsb) 10 0000 ? 32 10 0001 ? 31 ... ... 11 1111 ? 1 00 0000 0 00 0001 +1 ... ... 01 1110 +30 01 1111 +31 table 17. digital test pattern selection default values are shown highlighted. test_pat_sel[2:0] digital test pattern 000 off 001 mid code 010 min code 011 max code 100 toggle ?1111..1111?/?0000..0000? 101 custom test pattern 110 ?0101..0101? 111 ?1010..1010? table 18. output codes v inp ? v inm offset binary two?s complement gray code otr < ? 1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 1 ? 1 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 0 ? 0.99987793 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 0 ? 0.99975586 00 0000 0000 0010 00 0000 0000 0010 00 0000 0000 0011 0 ... ... ... ... 0 ? 0.00024414 01 1111 1111 1110 11 1111 1111 1110 01 0000 0000 0001 0
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 30 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.4 configuration pins (cfg0, cfg1, cfg2, cfg3) the configuration pins are only active as inputs at start-up. the values on those pins are read once to set up the device. then the pins become outputs (otra and otrb). any further modification must be applied via spi registers. each of these pins is internally connected to a 50 k ?? pull-down resistor. in case of harmonic sampling, it is recommended to connect externally a 1 k ?? pull-up resistor in order to start in power-down mode. [1] f: octets per frame clock cycle hd: high-density mode k: frame per multi-frame m: converters per device l: lane per converter device ? 0.00012207 01 1111 1111 1111 11 1111 1111 1111 01 0000 0000 0000 0 +0.00012207 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 0 +0.0.00024414 10 0000 0000 0001 00 0000 0000 0001 11 0000 0000 0001 0 ... ... ... ... 0 +0.99975586 11 1111 1111 1101 01 1111 1111 1101 10 0000 0000 0011 0 +0.99987793 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 0 +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0 > +1 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1 table 18. output codes ?continued v inp ? v inm offset binary two?s complement gray code otr table 19. jesd204b configuration table cfg 3 cfg 2 cfg 1 cfg 0 adc a adc b lane a lane b f [1] hd [1] k [1] m [1] l [1] 0000 on on on on 20922 0001 on on on off 4 0 5 2 1 0010 on on off on 40521 0 0 1 1 reserved 0 1 0 0 reserved 0101 on off on off 2 0 9 1 1 0110 on off off on 20911 0111off on on off 2 0 9 1 1 1000off on off on 20911 1001 on off on on 111712 1010off on on on 111712 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 off off off off 2 0 9 2 2
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 31 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs for all the configurations, the number of control bit per conversion sample (cs) is 1, the number of control words per frame clock cycle and link (cf) is 0, the number of samples transmitter per single converter per frame cycle (s) is 1 and the formula (f ? k) ? 17 is always verified.
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 32 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.5 serial peripheral interface (spi) 11.5.1 register description the adc1443d serial interface is a synchronous serial communication port, which allows easy interfacing with many commonly used microprocessors. it provides access to the registers controlling the operation of the chip. the register bits are either global or local functions: ? a global function operates over the full ic behavior. a local function operates on one or several previously selected channels only. if a channel is selected, the next write command in the local registers applies to the selected channel. the write command has no impact on channels that are not selected. this makes it possible to apply different configurations on each channel by first selecting a specific channel and then all the related settings. ? select only one channel during a read operation of the local registers. if several channels are selected, the read operation occurs on the channel a. programming all registers at the same time is required: ? the ic allows the storage of a set of settings for the addresses 06h to 23h, which enables the configuration of all registers simultaneously by setting bit transfer to high (see t able 39 ). this bit is autoclearing. this function can be disabled using spi (bit trans_dis in t able 39 ). the registers are then updated at each write operation. ? the transfer function does not apply to a read operation. the spi interface is configured as a 3-wire type: pin sdio is the bidirectional pin, pin sclk is the serial clock input and scs_n is the chip select pin. a low level on pin scs_n initiates each read/write operation. a minimum of 3 bytes is transmitted (two instruction bytes and at least 1 data byte; see t able 21 ). ? bit r/ w indicates whether it is a read (when high) or a write (when low) operation. ? bits w1 and w0 indicate the number of bytes to be transferred after both instruction bytes (see t able 21 ). table 20. instruction bytes for the spi bit: 7 (msb) 6 5 4 3 2 1 0 (lsb) description r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 21. number of data bytes transferred w1 w0 number of bytes transferred 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 or more bytes
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 33 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs ? bits a12 to a0 indicate the address of the register being accessed. if it concerns a multiple byte transfer, this address is the first register accessed. an address counter is increased to access subsequent addresses. the steps for a data transfer are: 1. communication starts with the first rising edge on pin sclk after a falling edge on pin scs_n. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the data. its length varies, but it is always a multiple of 8 bits. the msb is always sent first (for instruction and data bytes). 4. a rising edge on pin scs_n indicates the end on data transmission. fig 42. spi mode timing scs_n sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data)
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 34 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.5.2 start-up programing at power-up or after a reset by spi, the device needs a start-up programming for optimum performances. this initialization is done in 3 steps: those registers adjust some specific currents and timings. the programmed values should not be modified by the customer to ensure proper behavior over temperature and power supply variations. table 22. step 1 - clock divider programming register address (hex) value (hex) comment 0007 clk_div[2:0] in t able 29 in case of harmonic clocking table 23. step 2 - jesd204b initialization register address (hex) value (hex) comment 0803 cfg_setup [3:0] in t able 42 jesd204b configuration 0802 08 frame assembler subclock reset table 24. step 3 - adc core initialization register address (hex) adc1443d125 adc1443d160 adc1443d200 comment value (hex) value (hex) value (hex) 0100 d1 d1 d1 0200 01 01 01 00ff 80 80 80 registers updated on each write command 0102 07 07 07 0103 63 65 66 0012 10 10 10 0108 a7 a3 a3 010a c0 c0 c0 0154 01 01 01 0155 - - 03 0156 10 - d8 0160 - - ff 0161 17 07 17 0170 - - 10 0171 - - 10 0400 b0 b0 30 - - - wait for 400 ms 0004 08 08 08 - - - wait for 400 ms 0004 10 10 10 - - - wait for 400 ms 0004 20 20 20
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 35 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.5.3 register allocation map t able 25 shows an overview of all registers. table 25. register allocation map addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc control registers 0000h chip_rst rw sw_rst[7:0] 0000 0000 0001h chip_id r chip_id[7:0] [1] 0100 0011 0005h sw_rst r/w sw_rst - - - - - - - 0000 0000 0006h [2] op_mode r/w - - - - - - op_mode[1:0] [3] 0000 0000 0007h clk_cfg r/w - - - se_sel diff_se clk_div[2:0] 0000 0000 0008h internal_ ref r/w - - - - - intref[2:0] 0000 0000 0009h channel_ sel r/w - - - - - - adc_b adc_a 0000 1111 0011h output_ cfg r/w - - - - - data_ swap data_format[1:0] 0000 0000 0013h dig_offset r/w dig_offset[5:0] - - 0000 0000 0014h test_cfg_1 r/w - - - - - test_pat_sel[2:0] 0000 0000 0015h test_cfg_2 r/w test_pat_user[13:6] 0000 0000 0016h test_cfg_3 r/w test_pat_user[5:0] - - 0000 0000 0017h otr_cfg r/w - - - reserved fast_ otr fast_otr_det[2:0] 0001 0100 0043h dcs_ctrl r/w reserved[5:0] div_reset _pol div_rese t_sel 11000100 00ffh trans_cfg r/w trans_ dis transfer - - - - - - 0000 0000 jesd204a/jesd204b control 0801h ip_status r rxsync_ err_flg reserved[5:0] pll_lock 0100 0010 0802h ip_rst r/w sw_ rst - - - assembler_ sw_rst - - - 0000 0000 0803h ip_cfg_ setup r/w - - - - cfg_stp[3:0] 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 36 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 0805h ip_ctrl1 r/w reserved tristate_ cfg_pad syncb_ pol syncb_se en_ rxsync_err reserved[2:0] 0000 1001 0806h ip_ctrl2 r/w reserved[5:0] swp_ ?lane_1_2 swp_ adc_0_1 0011 0100 080bh ip_prbs_ ctrl r/w reserved[5:0] prbs_ type res 0000 0000 0810h jesd204b_c trl1 r/w lmfc_perio dic_rst lmfc_reset_ en - - - - - - 0000 0000 0811h jesd204b_c trl2 r/w dcs_periodi c_rst dcs_reset_e n - - - - - - 0000 0000 0812h jesd204b_c trl3 r/w - - - - sync_at_lmfc_e n - sync_captur e_path - 0000 0000 0816h ip_debug_ out1 r/w - - - - - - pat_out[9:8] 0000 0010 0817h ip_debug_ out2 r/w pat_out[7:0] 1010 1010 0818h ip_debug_ in1 r/w pat_in[15:8] 1110 0110 0819h ip_debug_ in2 r/w pat_in[7:0] 1110 1010 081bh ip_ testmode r/w reserved loop_ align dis_repl_ char byp_ align reserved[3:0] 0000 0000 081ch ip_expert_ door r/w key[7:0] 0000 0000 081eh sysref_cfg r/w - - - - sysref_en sysref_ se - - 0000 0000 0822h scr_l r/w scr_en reserved[5:0] l 0000 0001 0824h cfg_k r/w - - - k[4:0] 000x xxxx 086bh outbuf_a_ swing r/w reserved[4:0] swing[2:0] 0000 0010 086ch outbuf_b_ swing r/w reserved[4:0] swing[2:0] 0000 0010 table 25. register allocation map ?continued addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 37 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] the read-only and reserved registers. [2] the registers influenced by the transfer function. [3] the local registers. 0871h lane_a_0_ ctrl r/w reserved[2:0] lane_mode[1:0] lane_pol reserved lane_ pd 0000 0000 0872h lane_b_0_ ctrl r/w reserved[2:0] lane_mode[1:0] lane_pol reserved lane_ pd 0000 0000 0890h adc_a_0_ ctrl r/w - - adc_mode[1:0] - - - adc_ pd 0000 0000 0891h adc_b_0_ ctrl r/w - - adc_mode[1:0] - - - adc_ pd 0000 0000 table 25. register allocation map ?continued addr. (hex) register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 38 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.5.4 detailed register description the tables in this section contain detailed descriptions of the registers. 11.5.4.1 adc control registers [1] local register. table 26. chip_reset register (address 0000h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 sw_rst r/w - resets global and local registers for any value ?1? written at any bit (autoclear). table 27. sw_reset register (address 0005h) bit description default settings are shown highlighted. bit symbol access value description 7 sw_rst r/w resets global and local registers 0 no reset 1 performs a reset to the default values (autoclear) 6 to 0 - - - not used table 28. op_mode register (address 0006h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - not used 1 to 0 op_mode[1:0] [1] r/w operating mode for the selected channel 00 normal (power-up) 01 power-down 10 sleep 11 not used table 29. clk_cfg register (address 0007h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 - - - not used 4 se_sel r/w single-ended clock input pin selection 0 clkp 1 clkm 3 diff_se r/w differential/single-ended clock input selection 0 fully differential 1 single-ended
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 39 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] local register 2 to 0 clk_div[2:0] r/w clock divider selection 000 divide by 1 001 divide by 2 010 divide by 3 011 divide by 4 100 divide by 5 101 divide by 6 110 divide by 7 111 divide by 8 table 29. clk_cfg register (address 0007h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 30. internal_ref register (address 0008h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 to 0 intref[2:0] [1] r/w 000 see t able 1 1 table 31. channel_sel register (address 0009h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - not used 1 adc_b r/w channel b selection for next spi operation in local registers 0 not selected 1 selected 0 adc_a r/w channel a selection for next spi operation in local registers 0 not selected 1 selected table 32. output_cfg register (address 0011h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 data_swap [1] r/w output data bits swapped 0 no swapping 1 msbs swapped with lsbs
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 40 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] local register [1] local register [1] local register [1] local register [1] local register 1 to 0 data_format[1:0:] [1] r/w output data format 00 offset binary 01 two?s complement 10 gray code 11 offset binary table 32. output_cfg register (address 0011h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 33. dig_offset register (address 0013h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 dig_offset[7:0] [1] r/w 000000 see t able 16 1 to 0 - - - not used table 34. test_cfg_1 register (address 0014h) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 - - - not used 2 to 0 test_pat_sel[2:0] [1] r/w 000 see t able 17 table 35. test_cfg_2 register (address 0015h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 test_pat_user[13:6] [1] r/w 00000000 custom digital test pattern (bits 13 to 6) table 36. test_cfg_3 register (address 0016h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 test_pat_user[5:0] [1] r/w 000000 custom digital test pattern (bits 5 to 0) 1 to 0 - - - not used table 37. otr_cfg register (address 0017h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 - - - not used 4 reserved r/w 1 reserved
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 41 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] local register 3 fast_otr [1] r/w selection otr full-scale/ fast otr 0 otr full-scale 1 fast otr 2 to 0 fast_otr_det[2:0] [1] r/w 100 see t able 15 table 37. otr_cfg register (address 0017h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 38. dcs_ctrl register (address 0043h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 reserved r/w 110001 reserved 1 div_reset_pol r/w polarity of the dcs reset 0 falling edge (subclass 2) 1 rising edge (subclass 1) 0 div_reset_sel r/w dcs reset selection 0 syncbp/n is used (subclass 2) 1 sysrefp/n is used (subclass 1) table 39. trans_cfg register (address 00ffh) bit description default settings are shown highlighted. bit symbol access value description 7 trans_dis r/w disable transfer function 0 transfer function active 1 registers updated on a write command 6 transfer r/w updates the registers with the written settings 0 settings are stored 1 registers updated (autoclear) 5 to 0 - - - not used
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 42 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 11.5.4.2 jesd204a/jesd204b control registers table 40. ip_status register (address 0801h) bit description default settings are shown highlighted. bit symbol access value description 7 rxsync_err_flg r rx synchronization error 0 no error 1 synchronization error has occurred 6 to 1 reserved r/w 100001 reserved 0 pll_lock r jedec pll lock 0 unlocked 1 locked table 41. ip_reset register (address 0802h) bit description default settings are shown highlighted. bit symbol access value description 7 sw_rst r/w resets all jesd204b sub-blocks and registers 0 no reset 1 performs a reset to the default values (auto-clear) 6 to 4 - - - not used 3 assembler_sw_rst r/w resets rxsync_err_flg register bit and the frame assembler sub-block 0 no reset 1 performs a reset to the default values (auto-clear) 2 to 0 - - - not used table 42. ip_cfg_setup register (address 0803h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 - - - not used 3 to 0 cfg_setup[3:0] r/w 0000 see t able 43 table 43. jesd204b configuration table cfg_setup [3:0] adc a adc b lane a lane b f [1] hd [1] k [1] m [1] l [1] lane a serial frequency lane b serial frequency 0000 on on on on 20922 20 ? f s 20 ? f s 0001 on on on off40521 40 ? f s 0 0010 on on off on 40521 0 40 ? f s 0011 reserved 0100 reserved 0101 on off on off20911 20 ? f s 0 0110 on off off on 20911 0 20 ? f s 0111 off on on off20911 20 ? f s 0 1000 off on off on 20911 0 20 ? f s 1001 on off on on 1 1 17 1 2 10 ? f s 10 ? f s
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 43 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] f: octets per frame clock cycle hd: high-density mode k: frame per multi-frame m: converters per device l: lane per converter device for all the configurations, the number of control bit per conversion sample (cs) is 1, the number of control words per frame clock cycle and link (cf) is 0, the number of samples transmitter per single converter per frame cycle (s) is 1 and the formula (f ? k) ? 17 is always verified. 1010 off on on on 1 1 17 1 2 10 ? f s 10 ? f s 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 off off off off 20922 0 0 table 43. jesd204b configuration table ?continued cfg_setup [3:0] adc a adc b lane a lane b f [1] hd [1] k [1] m [1] l [1] lane a serial frequency lane b serial frequency table 44. ip_ctrl1 register (address 0805h) bit description default settings are shown highlighted. bit symbol access value description 7 reserved r/w 0 reserved 6 tristate_cfg_pad r/w cfg pad in tri-state mode 0 cfg pads in output mode 1 cfg pads in input mode; operating at power-up 5 syncb_pol r/w selects synchronization polarity 0 synchronization active low 1 synchronization active high 4 syncb_se r/w selects single-ended or differential synchronization 0 differential synchronization 1 single-ended synchronization on syncbp 3 en_rxsync_err r/w selects single-ended or differential synchronization 0 differential synchronization 1 single-ended synchronization on syncbp 2 to 0 reserved r/w 001 reserved table 45. ip_ctrl2 register (address 0806h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 reserved r/w 001101 reserved 1 swp_lane_a_b r/w swaps the lanes 0 no swap 1 lane a and b are inverted
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 44 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 0 swp_adc_a_b r/w swaps the adc at the input of the frame assembler 0 no swap 1 adc a and b are inverted table 45. ip_ctrl2 register (address 0806h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 46. ip_prbs_ctrl register (address 080bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 reserved r/w 000000 reserved 1 prbs_type r/w pseudo-random binary sequence (prbs) pattern selection 0 prbs-7; 1 + x 6 + x 7 1 prbs-23; 1 + x 18 + x 23 0 reserved r/w 0 reserved table 47. jesd204b_ctrl1 register (address 0810h) bit description default settings are shown highlighted. bit symbol access value description 7 lmfc_periodic_rst r/w lmfc mode definition 0 lmfc reset is done once 1 lmfc reset at each sysref or sync pulse 6 lmfc_reset_en r/w lmfc reset selection 0 syncbp/n is used (subclass 2) 1 sysrefp/n is used (subclass 1) 5 to 0 reserved r/w 00000 reserved table 48. jesd204b_ctrl2 register (address 0811h) bit description default settings are shown highlighted. bit symbol access value description 7 dcs_periodic_rst r/w dcs mode definition 0 dcs reset is done once 1 dcs reset at each sysref or sync pulse 6 dcs_reset_en r/w dcs reset selection 0 dcs reset is disabled 1 dcs reset is enabled 5 to 0 reserved r/w 00000 reserved
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 45 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs table 49. jesd204b_ctrl3 register (address 0812h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 reserved r/w 0000 reserved 3 sync_at_lmfc_en r/w defines the relation between sync and lmfc 0 sync is fetched directly (subclass 0) 1 sync is taken at next lmfc boundary (subclass 1 and subclass 2) 2 reserved r/w 0 reserved 1 sync_capture_path r/w selects sync mode 0 subclass 0 1 subclass 1 and subclass 2 0 reserved r/w 0 reserved table 50. ip_debug_out1 register (address 0816h) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - not used 1 to 0 pattern_out[9:8] r/w 10 2 most significant bits of output stage debug word (inserted just before serializer) table 51. ip_debug_out2 register (address 0817h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_out[7:0] r/w 1010 1010 8 least significant bits of output stage debug word (inserted just before serializer) table 52. ip_debug_in1 register (address 0818h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_in[15:8] r/w 1110 0110 8 most significant bits of input stage debug word (inserted in place of adc data) table 53. ip_debug_in2 register (address 0819h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pattern_in[7:0] r/w 1110 1010 8 least significant bits of input stage debug word (inserted in place of adc data) table 54. ip_testmode register (address 081bh) bit description default settings are shown highlighted. bit symbol access value description 7 reserved r/w 0 reserved 6 loop_align r/w continuous ila [1] sequence 0 normal operation 1 ila [1] repeated continuously
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 46 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs [1] ila = initial lane alignment sequence (see jesd204 jedec standard). 5 dis_repl_char r/w character replacement function selection 0 normal operation 1 character replacement disabled 4 byp_align r/w ila [1] sequence function selection 0 normal operation 1 ila [1] sequence disabled 3 to 0 reserved r/w 0000 reserved table 54. ip_testmode register (address 081bh) bit description ?continued default settings are shown highlighted. bit symbol access value description table 55. ip_expert_door register (address 081ch) bit description default settings are shown highlighted. bit symbol access value description 7 key[7:0] r/w 0000 0000 8-bit key (0x4a) to enable write access for scrambler (register 0828h) table 56. sysref_cfg register (address 081eh) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 reserved r/w 0000 reserved 3 sysref_en r/w enables sysrefp/n path 0 sysrefp/n path disabled 1 sysrefp/n path enabled 2 sysref_se r/w selects single-ended or differential sysref 0 sysrefp/syrefn are used as differential pair 1 sysrefp is used as single ended sysref input 1 to 0 reserved r/w 00 reserved table 57. scr_l register (address 0822h) bit description (ip_expert_door write access needed) default settings are shown highlighted. bit symbol access value description 7 scr_en r/w selects the scrambler function 0 scrambler disabled 1 scrambler enabled 6 to 1 reserved r/w 000000 reserved 0 l r/w lanes number minus 1 0 1 lane 1 2 lanes
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 47 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs table 58. cfg_k register (address 0824h) bit description (ip_expert_door write access needed, address 081ch) default settings are shown highlighted. bit symbol access value description 7 to 5 - - - not used 4 to 0 k[4:0] r/w 000x xxxx number of frames in a multi-frame. default value depends on the jesd204b configuration. table 59. ip_outbuf00_swing register (address 086bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 reserved[4:0] r/w 00000 reserved 2 to 0 swing[2:0] r/w configurable lane 0 output current 000 12 ma; ? 300 mv (p-p) 001 14 ma; ? 350 mv (p-p) 010 16 ma; ? 400 mv (p-p) 011 18 ma; ? 450 mv (p-p) 100 20 ma; ? 500 mv (p-p) 101 22 ma; ? 550 mv (p-p) 110 24 ma; ? 600 mv (p-p) 111 26 ma; ? 650 mv (p-p) table 60. ip_outbuf01_swing register (address 086ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 3 reserved[4:0] r/w 00000 reserved 2 to 0 swing[2:0] r/w configurable lane 1 output current 000 12 ma; ? 300 mv (p-p) 001 14 ma; ? 350 mv (p-p) 010 16 ma; ? 400 mv (p-p) 011 18 ma; ? 450 mv (p-p) 100 20 ma; ? 500 mv (p-p) 101 22 ma; ? 550 mv (p-p) 110 24 ma; ? 600 mv (p-p) 111 26 ma; ? 650 mv (p-p) table 61. ip_lane_a_0_ctrl register (address 0871h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 reserved[2:0] r/w 000 reserved 4 to 3 lane_mode[1:0] r/w debug option directly before serializer 00 normal mode, adc path 01 0/1 toggle sent over the lanes 10 ip_debug_out value sent over the lanes 11 10-bit prbs pattern is sent over the lane
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 48 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 2 lane_pol r/w selects lane polarity 0 no inversion 1 lane polarity p/n inverted 1 reserved r/w 0 reserved 0 lane_pd r/w selects lane power mode 0 lane is powered-up 1 lane is powered-down table 61. ip_lane_a_0_ctrl register (address 0871h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 62. ip_lane_b_0_ctrl register (address 0872h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 reserved[2:0] r/w 000 reserved 4 to 3 lane_mode[1:0] r/w debug option directly before serializer 00 normal mode, adc path 01 0/1 toggle sent over the lanes 10 ip_debug_out value sent over the lanes 11 10-bit prbs pattern is sent over the lane 2 lane_pol r/w selects lane polarity 0 no inversion 1 lane polarity p/n inverted 1 reserved r/w 0 reserved 0 lane_pd r/w selects lane power mode 0 lane is powered-up 1 lane is powered-down table 63. ip_adc_a_0_ctrl register (address 0890h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 reserved r/w 00 reserved 5 to 4 adc_mode[1:0] r/w debug option at adc output 00 normal mode, adc path 01 normal mode, adc path 10 ip_debug_in value sent i.s.o. adc data 11 16-bit prbs pattern is sent i.s.o. adc data 3 to 1 reserved r/w 000 reserved 0 adc_pd r/w selects adc power mode 0 adc is powered-up 1 adc is powered-down
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 49 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs table 64. ip_adc_b_0_ctrl register (address 0891h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 reserved r/w 00 reserved 5 to 4 adc_mode[1:0] r/w debug option at adc output 00 normal mode, adc path 01 normal mode, adc path 10 ip_debug_in value sent i.s.o. adc data 11 16-bit prbs pattern is sent i.s.o. adc data 3 to 1 reserved r/w 000 reserved 0 adc_pd r/w selects adc power mode 0 adc is powered-up 1 adc is powered-down
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 50 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 12. package outline fig 43. package outline psc-4449 (vfqfpn56)
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 51 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs 13. abbreviations table 65. abbreviations acronym description adc analog-to-digital converter cdma code division multiple access dav data valid esd electrostatic discharge fft fast fourier transform gsm global system for mobile communications ila initial lane alignment imd3 third order intermodulation product lsb least significant bit lte long-term evolution lvds ddr low voltage differential signaling double data rate lvpecl low-voltage positive emitter-coupled logic mimo multiple input multiple output msb most significant bit otr out-of-range sfdr spurious-free dynamic range spi serial peripheral interface snr signal-to-noise ratio td-scdma time division-synchronous code division multiple access wcdma wideband code division multiple access wimax worldwide interoperability for microwave access tclk period of the sampling clock
adc1443d_ser ? idt 2014. all rights reserved. product data sheet rev. 4.4 ? 6 june 2014 52 of 53 integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs contact information 6024 silver creek valley road san jose, california 95138 14. revision history table 66. revision history document id release date data sheet status change notice supersedes adc1443d_ser v.4.4 20140606 product data sheet - parameter k added - offset error updated adc1443d_ser v.4.3 adc1443d_ser v.4.3 20131113 product data sheet registers updated adc1443d_ser v.4.2 adc1443d_ser v.4.2 20130402 product data sheet new package outline adc1443d_ser v.4.1 adc1443d_ser v.4.1 20130227 product data sheet - adc1443d_ser v.4.0 adc1443d_ser v.4.0 20130213 product data sheet - adc1443d_ser v.3.6 adc1443d_ser v.3.6 20130208 data sheet - adc1443d_ser v.3.5 adc1443d_ser v.3.5 20130111 data sheet - adc1443d_ser v.3.4 adc1443d_ser v.3.4 20121010 data sheet - adc1443d_ser v.3.3 adc1443d_ser v.3.3 20120926 objective data sheet - adc1443d_ser v.3.2 adc1443d_ser v.3.2 20120918 objective data sheet - adc1443d_ser v.3.1 adc1443d_ser v.3.1 20120911 objective data sheet - adc1443d_ser v.3.0 adc1443d_ser v.3.0 20120901 objective data sheet - adc1443d_ser v.2.0 modifications: ? text and drawings updated throughout entire data sheet. adc1443d_ser v.2.0 20120630 objective data sheet - adc1443d_ser v.1.1 adc1443_ser v.1.1 20110928 objective data sheet - adc1443d_ser v.1 adc1443d_ser v.1 20110901 objective data sheet - -
integrated device technology adc1443d series dual 14-bit adc; 125, 160 or 185 msps; jesd204a/b serial outputs disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications de scribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without noti ce. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suit ability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written a greement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright, 2014. all rights reserved. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 start-up configuration. . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 thermal characteristics. . . . . . . . . . . . . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.2.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.2.2 sysrefp/n and syncbp/n timings. . . . . . . 12 10.2.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10.3 typical dynamic performances . . . . . . . . . . . . 14 10.3.1 typical fft at 122.88 msps . . . . . . . . . . . . . . 14 10.3.2 typical fft at 153.6 msps . . . . . . . . . . . . . . . 15 10.3.3 typical fft at 184.32 msps . . . . . . . . . . . . . . 16 10.3.4 typical snr performances . . . . . . . . . . . . . . . 17 10.3.5 typical sfdr performances. . . . . . . . . . . . . . 18 10.3.6 typical imd3 performances . . . . . . . . . . . . . . 19 11 application information. . . . . . . . . . . . . . . . . . 20 11.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.1 input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.2 common-mode input voltage (v i(cm) ) . . . . . . . 20 11.1.3 pin vcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.4 programmable full-scale . . . . . . . . . . . . . . . . . 21 11.1.5 anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 21 11.1.6 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.2.1 drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.2.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 24 11.2.3 jesd204b harmonic clocking . . . . . . . . . . . . 24 11.2.4 jesd204b deterministic latency (pins sysrefn and sysrefp or syncbp and syncbn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.3 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 26 11.3.1 digital output buffers . . . . . . . . . . . . . . . . . . . 26 11.3.2 jesd204a/jesd204b serializer . . . . . . . . . . 26 11.3.2.1 digital jesd204a/jesd204b formatter. . . . . 26 11.3.2.2 scrambler (scr_en). . . . . . . . . . . . . . . . . . . 28 11.3.3 out-of-range (otr) . . . . . . . . . . . . . . . . . . . 28 11.3.4 digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.3.5 test patterns. . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3.6 output data format selection . . . . . . . . . . . . . 29 11.3.7 output codes versus input voltage. . . . . . . . . 29 11.4 configuration pins (cfg0, cfg1, cfg2, cfg3) 30 11.5 serial peripheral interface (spi) . . . . . . . . . . 32 11.5.1 register description . . . . . . . . . . . . . . . . . . . . 32 11.5.2 start-up programing . . . . . . . . . . . . . . . . . . . . 34 11.5.3 register allocation map . . . . . . . . . . . . . . . . . 35 11.5.4 detailed register description. . . . . . . . . . . . . . 38 11.5.4.1 adc control registers . . . . . . . . . . . . . . . . . . . 38 11.5.4.2 jesd204a/jesd204b control registers . . . . 42 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 49 13 abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 51 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

▲Up To Search▲

Price & Availability of ADC1443D200HD

	To Download ADC1443D200HD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .